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INTEGRATED CIRCUITS
DATA SHEET
TDA8785 8-bit high-speed analog-to-digital converter with gain and offset controls
Product specification Supersedes data of 1996 Jan 17 File under Integrated Circuits, IC02 1997 Dec 18
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
FEATURES * 8-bit analog-to-digital converter (ADC) * 8-bit digital-to-analog converter (DAC) * Sampling rate up to 30 Msps for both ADC and DAC * Binary or two's complement 3-state TTL outputs * TTL compatible inputs and outputs * 100 MHz variable gain amplifier (0 to 20 dB) externally controlled * All analog inputs and outputs are differential (can also be used in single-ended format) * Analog input signal from 0.1 to 1.0 V (p-p) differential * Offset amplifier with: - Slow offset control (250 mV) - Fast offset control (500 mV) eventually driven by internal DAC. * ADC output code of 8 (typ.) when analog input signal and offset correction inputs are 0 V QUICK REFERENCE DATA SYMBOL VCCA1 VCCA2 VCCD VCCO ICCA ICCD ICCO INL DNL fclk(max) B Ptot PARAMETER analog supply voltage 1 analog supply voltage 2 digital supply voltage TTL output supply voltage analog supply current digital supply current TTL output supply current integral non-linearity differential non-linearity maximum clock frequency controlled gain amplifier bandwidth total power dissipation 0 to 20 dB gain; ramp input 0 to 20 dB gain; ramp input ADC and DAC CONDITIONS MIN. 4.75 4.75 4.75 4.75 - - - - - 30 - - TYP. 5.0 5.0 5.0 5.0 80 30 9 0.7 0.2 - 100 600 GENERAL DESCRIPTION
TDA8785
* Gain, slow offset control inputs and DAC output swing of 1.5 V (p-p) range (2.75 0.75 V) * 2.75 V reference voltage * Internal references for ADC and DAC. APPLICATIONS * CCD type of systems * Scanner * Copier * Video acquisition.
The TDA8785 is an 8-bit analog-to-digital converter with gain and offset controls for the input signal. An internal 8-bit DAC provides fast offsets control.
MAX. 5.25 5.25 5.25 5.25 - - - 1.8 0.7 - - -
UNIT V V V V mA mA mA LSB LSB MHz MHz mW
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION
TDA8785H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
1997 Dec 18
2
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
BLOCK DIAGRAM
TDA8785
handbook, full pagewidth
VCCA1 1
VCCA2 2
AGND1 3
AGND2 4
B 6
VRB Vref 7
DEC2 OF DEC1 5 35 34
36
REGULATORS Vi(p) Vi(n) VSOFF(p) VSOFF(n) VFOFF(p) VFOFF(n) VFSAD(p) VFSAD(n) 43 44 37 38 42 41 39 40 VCCA 150 VDACO(p) VDACO(n) VFSDAC(p) VFSDAC(n) 9 8 10 11 DAC CLOCK DRIVER 8 12 to 19 DA7 to DA0 20 CLKDAC CLOCK DRIVER 22 CLKADC 23 21
MBG681
OFFSET AMPLIFIER
GAIN
ADC
8
TTL OUTPUTS
26 to 33 8 AD0 to AD7
25 24
150
VCCO OGND
TDA8785
VCCD DGND
Fig.1 Block diagram.
1997 Dec 18
3
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
PINNING SYMBOL VCCA1 VCCA2 AGND1 AGND2 DEC2 B VRB VDACO(n) VDACO(p) VFSDAC(p) VFSDAC(n) DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CLKDAC DGND CLKADC VCCD PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 DESCRIPTION analog supply voltage 1 (+5 V) analog supply voltage 2 (+5 V) analog ground 1 analog ground 2 decoupling input 2 bandwidth adjustment node input ADC reference voltage output bottom (decoupling) DAC negative voltage output DAC positive voltage output DAC full-scale positive control voltage input DAC full-scale negative control voltage input DAC TTL input; bit 7 (MSB) DAC TTL input; bit 6 DAC TTL input; bit 5 DAC TTL input; bit 4 DAC TTL input; bit 3 DAC TTL input; bit 2 DAC TTL input; bit 1 DAC TTL input; bit 0 (LSB) DAC clock input digital ground ADC clock input digital supply voltage (+5 V) Vi(p) Vi(n) 43 44 VFOFF(p) 42 SYMBOL OGND VCCO AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 OF DEC1 Vref VSOFF(p) VSOFF(n) VFSAD(p) VFSAD(n) VFOFF(n) PIN 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
TDA8785
DESCRIPTION output ground output supply voltage (+5 V) output data; bit 0 (LSB) output data; bit 1 output data; bit 2 output data; bit 3 output data; bit 4 output data; bit 5 output data; bit 6 output data; bit 7 (MSB) output format input decoupling input 1 reference voltage output (2.75 V) slow offset amplifier positive voltage input slow offset amplifier negative voltage input gain control positive voltage input gain control negative voltage input fast offset amplifier negative voltage input fast offset amplifier positive voltage input analog positive voltage input analog negative voltage input
1997 Dec 18
4
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
TDA8785
40 VFSAD(n)
39 VFSAD(p)
38 VSOFF(n)
handbook, full pagewidth
37 VSOFF(p)
42 VFOFF(p)
41 VFOFF(n)
35 DEC1
44 Vi(n)
43 Vi(p)
36 Vref
VCCA1 VCCA2 AGND1 AGND2 DEC2 B VRB VDACO(n) VDACO(p)
1 2 3 4 5 6 7 8 9
34 OF
33 AD7 32 AD6 31 AD5 30 AD4 29 AD3
TDA8785
28 AD2 27 AD1 26 AD0 25 VCCO 24 OGND 23 VCCD
VFSDAC(p) 10 VFSDAC(n) 11 DA7 12 DA6 13 DA5 14 DA4 15 DA3 16 DA2 17 DA1 18 DA0 19 CLKDAC 20 DGND 21 CLKADC 22
MBG680
Fig.2 Pin configuration.
1997 Dec 18
5
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
FUNCTIONAL DESCRIPTION The TDA8785 is composed of an 8-bit ADC (30 Msps), a wide-band gain amplifier, an input offset amplifier and an 8-bit dynamic adjustment DAC. Input signal Two input pins are provided to apply a differential input signal with a wide range (100 to 1000 mV differential). It is also possible to apply a single signal by setting a DC voltage on one of the differential pins and supplying the signal to the other. Controlled gain amplifier The gain amplifier is used to adjust the wide input signal range to the fixed ADC input range of 1 V (p-p). A large gain of 20 dB can be achieved with low-noise behaviour and a large bandwidth of 100 MHz to correctly amplify square type signals with step edges. Using pin 6, it is possible to reduce the internal bandwidth of the gain amplifier via an external capacitor and thus improve its noise behaviour. The gain amplifier is controlled via an external differential voltage (single input can also be applied). Input offset amplifier and adjustment DAC The Input offset amplifier contains two different control inputs (which can also be single): * Slow offset control, for slow variation characteristics (e.g. temperature, supply voltage, etc.) * Fast offset control, for correction related to the clock rate. Slow offset control is carried out by an external voltage while fast offset control is digitally carried out via the internal 8-bit DAC with external connections of the respective pins VDACO(n), VDACO(p), VFOFF(n) and VFOFF(p).
TDA8785
The internal 8-bit DAC operates at the ADC clock rate to allow dynamic corrections on the input signal chain based on the signal processing information carried out after the digital conversion. The output voltage amplitude of the DAC can be controlled via a different input voltage (which can also be single) in a range of 25% with a 150 DAC output load. The DAC can also be used for the gain or the slow offset control with some external DC voltage adaptations and can be considered as a separate function of the ADC chain. The DAC can be used independently, for example as a video DAC. 8-bit ADC The 8-bit ADC converts a signal of 1 V (p-p) from the controlled gain amplifier into an 8-bit coded digital word at a maximum rate of 30 Msps. Its reference voltage is supplied by the general voltage regulator. The output data format can either be binary, two's complement or 3-state by selecting pin OF. When all the differential inputs on the offset amplifier (VSOFF(p), VSOFF(n), VFOFF(n), VFOFF(p), Vi(p) and Vi(n)) are at 0 V (equivalent to both inputs short-circuited), the output code of the ADC is code 8. Internal voltage regulator An internal voltage regulator provides all the references for the different blocks. A stable 2.75 V voltage reference output is provided for use in the application environment. One application is to connect all the slow control inputs (VFSDAC(p), VFSDAC(n), VSOFF(p), VSOFF(n), VFSAD(p) and VFSAD(n)) to this reference, either to their two differential inputs to get the nominal settings or to one of the differential inputs to have easy single-input control. All these control inputs have the same control range.
1997 Dec 18
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Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output supply voltage supply voltage difference between VCCA and VCCD VCCD and VCCO VCCA and VCCO Vi Vclk(p-p) Io Tstg Tamb Tj input voltage output current storage temperature operating ambient temperature junction temperature -1.0 -1.0 -1.0 referenced to AGND -0.3 - -55 0 - CONDITIONS MIN. -0.3 -0.3 -0.3
TDA8785
MAX. +7.0 +7.0 +7.0 +1.0 +1.0 +1.0 +7.0 VCCD 6 +150 70 150
UNIT V V V V V V V V mA C C C
clock input voltage for switching (peak-to-peak value) referenced to DGND -
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 75 UNIT K/W
1997 Dec 18
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Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
CHARACTERISTICS VCCA1 = VCCA2 = VCCD = VCCO = 4.75 to 5.25 V; AGND, DGND and OGND short-circuited together; VCCA to VCCD = VCCD to VCCO = VCCA to VCCO = -0.25 to +0.25 V; Tamb = 0 to 70 C; typical values measured at VCCA = VCCD = VCCO = 5 V and Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA1 VCCA2 VCCD VCCO ICCA ICCD ICCO analog supply voltage 1 analog supply voltage 2 digital supply voltage TTL output supply voltage analog supply current digital supply current TTL output supply current 4.75 4.75 4.75 4.75 - - - 5.0 5.0 5.0 5.0 80 37 9 PARAMETER CONDITIONS MIN. TYP.
TDA8785
MAX. UNIT
5.25 5.25 5.25 5.25 - - -
V V V V mA mA mA
Reference voltages (pins Vref and VRB) Vo(ref) Vline Io(L) VRB Voffset(B) VADC output reference voltage line regulation voltage output load current reference voltage output bottom (decoupling) offset voltage bottom ADC reference voltage difference code 0 - VRB between code 0 and 255 VCCA = 4.75 to 5.25 V 2.60 - -0.5 - - - 2.75 4 - VCCA - 2.5 250 1 2.90 - +0.5 - - - V mV mA V mV V
Analog inputs (pins Vi(p) and Vi(n)); see Table 1 Vi(diff)(p-p) VI Ii Zi Ci differential input voltage Vi(p) - Vi(n) (peak-to-peak value) DC input voltage input current input impedance input capacitance 0 dB gain 20 dB gain - - 2.5 - - - - - - - - - - 1000 100 3.0 7 20 1 - - 3.5 - - - - - - - - - - mV mV V A k pF
Fast offset amplifier inputs (pins VFOFF(p) and VFOFF(n)); DC parameters VFOFF(p) VFOFF(n) VI Ii Zi Ci positive input voltage negative input voltage DC input voltage input current input impedance input capacitance 0 dB gain 20 dB gain 0 dB gain 20 dB gain 500 50 500 50 4 20 1 mV mV mV mV V A k pF
VCCA - 0.75 VCCA - 0.25 VCCA
1997 Dec 18
8
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA8785
MAX. UNIT
Slow offset amplifier inputs (pins VSOFF(p) and VSOFF(n)) gain amplifier at 0 dB; note 1 Voffset(ADC) offset voltage at ADC input VSOFF(p) = 2 V; VSOFF(n) = 2.75 V VSOFF(p) = 2.75 V; VSOFF(n) = 2.75 V VSOFF(p) = 3.5 V; VSOFF(n) = 2.75 V Ii input current Offset reference code; Tamb = 25 C OFSRE OFSER offset reference (ADC output code) offset reference error on code 8 Vi(p) = Vi(n); VFOFF(p) = VFOFF(n); VSOFF(p) = VSOFF(n); amplifier gain set at 0 dB - -15 8 0 - +15 code code - - - - -0.25 0 0.25 10 - - - - V V V A
Gain control inputs (pins VFSAD(p) and VFSAD(n)); see Fig.7 Gv(min) Gv(max) Ii minimum voltage gain maximum voltage gain input current VFSAD(p) = 2 V; VFSAD(n) = 2.75 V VFSAD(p) = 3.5 V; VFSAD(n) = 2.75 V - 20 - - - 10 0 - - dB dB A
DAC full-scale control inputs (pins VFSDAC(p) and VFSDAC(n)) 150 output load on pins VDACO(p) and VDACO(n); see Table 3 VDACO(n) DAC negative output voltage (pin 8) code 0 at DAC inputs - VCCA VCCA - 0.4 - - V V code 255 at DAC inputs; - VFSDAC(p) = 2 V; VFSDAC(n) = 2.75 V code 255 at DAC inputs; - VFSDAC(p) = 2.75 V; VFSDAC(n) = 2.75 V code 255 at DAC inputs; - VFSDAC(p) = 3.5 V; VFSDAC(n) = 2.75 V Ii Zi input current - - - - - Bandwidth adjustment node input (pin B); see Fig.6 input impedance 500 - - 0.8 1.0 LSB LSB 8-bit DAC; fclk = 30 MHz, ramp input; Tamb = 25 C Zo INL DNL output impedance integral non-linearity differential non-linearity 150 0.4 0.4
VCCA - 0.5
-
V
VCCA - 0.6
-
V
1
-
A
1997 Dec 18
9
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
SYMBOL PARAMETER CONDITIONS MIN. - - - - 4 4.5 - - 1.20 -130 300 - - - - - 0.7 0.2 TYP.
TDA8785
MAX. UNIT
Digital inputs (pins CLKDAC, CLKADC and DA7 to DA0) VIL VIH IIL IIH Zi Ci VIL VIH Vi(Z) IIL IIH VOL VOH fclk(max) tCPH tCPL INL DNL S/N LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance VIL = 0.4 V VIH = 2.7 V fclk = 10 MHz fclk = 10 MHz 0 2.0 -400 - - - 0.8 - 100 - - V A A k pF VCCD V
ADC output format (pin OF); see Table 2 LOW-level input voltage HIGH-level input voltage input voltage in high impedance state LOW-level input current HIGH-level input current VIL = 0.4 V Vclk = 2.7 V IOL = 2 mA IOH = -0.4 mA note 2 0 2.6 - -370 - 0.2 - - 450 V V A A VCCD V
ADC digital outputs LOW-level output voltage HIGH-level output voltage 0 2.4 0.6 V VCCO V - - - 1.8 0.7 MHz ns ns
ADC and DAC switching; see Fig.4 maximum clock frequency clock pulse width HIGH clock pulse width LOW 30 12 12 -
Analog processing; note 3 integral non-linearity differential non-linearity signal-to-noise ratio (without harmonics) ramp input (full-scale); 0 to 20 dB gain ramp input (full-scale); 0 to 20 dB gain fi = 2 MHz 0 dB gain 10 dB gain 20 dB gain B bandwidth -3 dB - - - - 47 45 43 100 - - - - dB dB dB MHz LSB LSB
1997 Dec 18
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Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
SYMBOL Timing ADC DIGITAL OUTPUTS (CL = 15 pF) tds th td tSU; DAT tHD; DAT tS RSA sampling delay time output hold time output delay time - 7 - note 4 note 4 RL = 150 ; CL = 15 pF note 5; see Fig.8 - - - - -0.3 - - 1.5 - - - - 8 0.1 PARAMETER CONDITIONS MIN. TYP.
TDA8785
MAX. UNIT
- - 16 - 2 - 2.5
ns ns ns
DAC OUTPUTS (PINS VDACO(p) AND VDACO(n)) data set-up time data hold time DAC setting time (10 to 90%) residual setting accuracy ns ns ns %
3-STATE OUTPUT DELAY TIMES (see Fig.5) tdZH tdZL tdHZ tdLZ Notes 1. Vos is proportional to the amplifier gain. For instance, Vos at 20 dB is the one indicated at 0 dB multiplied by 10. 2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and analog grounds is recommended. 3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; fclk = 30 MHz; no external filtering on pin 6 (B). 4. The data set-up time (tSU; DAT) is the minimum period preceding the rising edge of the clock, that the input data must be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the rising edge and still be recognized. The data set hold time (tHD; DAT) is the minimum period following the rising edge of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that the data may be released prior to the rising edge and still be recognized. 5. The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour. The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time tX. enable HIGH enable LOW disable HIGH disable LOW 15 15 13 10 20 20 20 20 ns ns ns ns
1997 Dec 18
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Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
Table 1
TDA8785
Output coding and input voltage (typical values; referenced to AGND, Vi(p) - Vi(n) = 1 V (p-p), 0 dB gain, no offset correction Vi(p) - Vi(n) 0.032 -0.032 - - 0 - - 0.968 >0.968 BINARY OUTPUT BITS D7 0 0 0 . 0 . 1 1 1 D6 0 0 0 . 0 . 1 1 1 D5 0 0 0 . 0 . 1 1 1 D4 0 0 0 . 0 . 1 1 1 D3 0 0 0 . 1 . 1 1 1 D2 0 0 0 . 0 . 1 1 1 D1 0 0 0 . 0 . 1 1 1 D0 0 0 1 . 0 . 0 1 1 TWO'S COMPLEMENT OUTPUT BITS D7 1 1 1 . 1 . 0 0 0 D6 0 0 0 . 0 . 1 1 1 D5 0 0 0 . 0 . 1 1 1 D4 0 0 0 . 0 . 1 1 1 D3 0 0 0 . 1 . 1 1 1 D2 0 0 0 . 0 . 1 1 1 D1 0 0 0 . 0 . 1 1 1 D0 0 0 1 . 0 . 0 1 1
STEP Underflo w 0 1 . 8 . 254 255 Overflow Table 2
OF input coding OF 0 1 open circuit; note 1 AD0 to AD7 active, two's complement high impedance active, binary
Note 1. Use C 10 pF to DGND. Table 3 Input coding and DAC output voltages (typical values; referenced to VCCA regardless of the offset voltage); VFSDAC(p) = VFSDAC(n) BINARY INPUT DATA CODE DA7 0 1 . 128 . 254 255 0 0 . 1 . 1 1 DA6 0 0 . 0 . 1 1 DA5 0 0 . 0 . 1 1 DA4 0 0 . 0 . 1 1 DA3 0 0 . 0 . 1 1 DA2 0 0 . 0 . 1 1 DA1 0 0 . 0 . 1 1 DA0 0 1 . 0 . 0 1 DAC OUTPUT VOLTAGES (V) ZL = 10 k VDACO(p) -1.0 - . -0.5 . - 0 VDACO(n) 0 - . -0.5 . - -1.0 ZL = 150 VDACO(p) -0.5 - . -0.25 . - 0 VDACO(n) 0 - . -0.25 . - -0.5
1997 Dec 18
12
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
TDA8785
handbook, full pagewidth
t SU; DAT
t HD; DAT 3.0 V
input data
stable
1.4 V 0V
3.0 V CLKDAC
MBG682
1.4 V 0V
The shaded areas indicate when the input data may change and be correctly registered. Data input update must be completed within 0.3 ns, after the first rising edge of the clock (tSU; DAT is negative; -0.3 ns). Data must be held at least 2 ns after the rising edge (tHD; DAT = +2 ns).
Fig.3 Data set-up and hold times (DAC).
handbook, full pagewidth
t CPL t CPH CLKADC 1.4 V
sample N
sample N + 1
sample N + 2
Vi(p) - Vi(n)
t ds DATA AD0 to AD7 DATA N-2 DATA N-1 td
th 2.4 V DATA N DATA N+1
MBG683
1.4 V 0.4 V
Fig.4 Timing diagram.
1997 Dec 18
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Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
TDA8785
handbook, full pagewidth
V CCD OF 50 % 1.15 V t dHZ HIGH 90 % output data t dLZ t dZL HIGH Z output data LOW 10 % TEST V CCD 3.3 k TDA8785 15 pF OF S1 t dLZ t dZL t dHZ t dZH S1 VCCD VCCD GND GND
MBG684
t dZH
50 % HIGH Z
50 %
fOF = 100 kHz.
Fig.5 Timing diagram and test conditions of 3-state output delay time.
102 handbook, halfpage f-3 dB (MHz) 10
(2) (1)
MBG691
48 S/N (dB)
handbook, halfpage
25
MBG692
Gv (dB) 20
46 15
10 1 44 5
10-1 10-1
1
10
102
CB (pF)
42 103
0 -0.75
-0.50
-0.25
0 0.50 0.75 0.25 VFSAD(p) - VFSAD(n) (V)
(1) f-3 dB. (2) Signal-to-noise ratio. The controlled gain amplifier is set at 20 dB gain.
Fig.6
Gain amplifier bandwidth and acquisition chain S/N ratio as a function of the external capacitance on pin 6.
Fig.7
Typical amplifier gain (Gv) as a function of the differential input voltage; VFSAD(p) - VFSAD(n).
1997 Dec 18
14
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
TDA8785
handbook, full pagewidth
MBK516
VDACO (%) 100 90 RSA
10 0 ts tx t
Fig.8 DAC time response when a full-scale step is applied.
INTERNAL PIN CONFIGURATIONS
handbook, halfpage
VCCO
ook, halfpage
VCCA
VFSDAC(p), VSOFF(p), VFSAD(p), VFOFF(p), Vi(p) or VFSDAC(n), VSOFF(n), VFSAD(n), VFOFF(n), Vi(n) AD0 to AD7 AGND DGND
MBG685 MBG686
Fig.9 TTL data outputs.
Fig.10 Analog inputs.
1997 Dec 18
15
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
TDA8785
dbook, halfpage
andbook, halfpage
VCCA 500 B
VCCA
RLAD VRB
AGND
MBG687
AGND
MBG688
Fig.11 Bandwidth input (B).
Fig.12 VRB.
ndbook, halfpage
VCCD 40 k
handbook, halfpage
DA7 to DA0 or CLKDAC or CLKADC
200 VDACO(p)
150
150 VDACO(n)
DGND
MBG689
MBG690
Fig.13 DAC inputs.
Fig.14 DAC outputs.
1997 Dec 18
16
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
APPLICATION INFORMATION
TDA8785
handbook, full pagewidth
B AGND1 VCCA1 1 VCCA2 2 3 4 AGND2 2 pF 6
VCCA1 3.3 nF VRB 7
Vref
DEC2 DEC1 OF 10 pF 5 100 nF 35 1 nF 34
100 nF 36
REGULATORS Vi(p) Vi(n) VSOFF(p) VSOFF(n) VFOFF(p) VFOFF(n) VFSAD(p) VFSAD(n) 150 150 VDACO(p) VDACO(n) VFSDAC(p) VFSDAC(n) 43 44 37 38 42 41 39 40 VCCA 150 9 8 10 11 DAC CLOCK DRIVER 8 12 to 19 DA7 to DA0 20 CLKDAC CLOCK DRIVER 22 CLKADC 23 21
MBG693
OFFSET AMPLIFIER
GAIN
ADC
8
26 to 33 TTL OUTPUTS 8
AD0 to AD7
VCCA
25 24
150
VCCO OGND
TDA8785
VCCD DGND
Fig.15 Application diagram.
1997 Dec 18
17
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
TDA8785
SOT307-2
c
y X
A 33 34 23 22 ZE
e E HE wM bp pin 1 index 44 1 bp D HD wM 11 ZD B vM B vMA 12 detail X A A2 (A 3) Lp L
A1
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.10 A1 0.25 0.05 A2 1.85 1.65 A3 0.25 bp 0.40 0.20 c 0.25 0.14 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.8 HD 12.9 12.3 HE 12.9 12.3 L 1.3 Lp 0.95 0.55 v 0.15 w 0.15 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 10 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT307-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1997 Dec 18
18
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
TDA8785
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: *A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. *The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Dec 18
19
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8785
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Dec 18
20
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
NOTES
TDA8785
1997 Dec 18
21
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
NOTES
TDA8785
1997 Dec 18
22
Philips Semiconductors
Product specification
8-bit high-speed analog-to-digital converter with gain and offset controls
NOTES
TDA8785
1997 Dec 18
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/02/pp24
Date of release: 1997 Dec 18
Document order number:
9397 750 03005

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